Is There a ZTC Biasing Point in the Leading-Edge FET Intrinsic Gain g_mr_DS?

Using a Design-Oriented 5 DC-Parameter MOSFET model along with simulation results derived from advanced 16 nm technology, we demonstrate that a zero temperature coefficient (ZTC) bias point does not exist in the intrinsic gain of the transistor, represented by <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$g_{m}r_{ds}$</tex>. Instead, it was found that a ZTC zone is present when the transistor operates in a well- saturated condition. Although some temperature dependence persists within this ZTC zone, it is characterized by a low complementary to absolute temperature (CTAT) behavior, as indicated by an effective temperature coefficient <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(TC_{eff})$</tex> under 100 <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\text{ppm}/\circ \mathrm{c}$</tex>, i.e., 0.01 % per each <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1^{0}\mathrm{C}$</tex>. Furthermore, both theo-retical analysis and simulation results reveal that the ZTC zone in both strong and weak inversion does not manifest in triode operation due to the pronounced CTAT behavior of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$r_{ds}$</tex>, which is not adequately compensated by the proportional to absolute temperature (PTAT) behavior of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$g_{m}$</tex>. This research highlights the complexities of temperature dependence in MOSFET operations and introduces significant insights into transistor behavior at the nanoscale.