Block-Wise MLSE Processing with Small Overlap for Digital Coherent Parallel Implementation

We investigate the convergence of path metrics in Viterbi algorithm to identify the number of overlapped symbols for parallelization of MLSE. 64-Gbaud 16-QAM with 23-GHz bandwidth requires only three overlapped symbols in the parallelization scheme.

Authors

Shuto Yamamoto (ORCID: https://orcid.org/0000-0003-2027-2751)
Etsushi Yamazaki (ORCID: https://orcid.org/0000-0001-5373-353X)
Hiroki Taniguchi (ORCID: https://orcid.org/0000-0001-9339-9708)
Y. Nakajima

Institutions

NTT (Japan) (JP)

Publication Details

Published: 2025-06-29
DOI: https://doi.org/10.23919/oecc/psc62146.2025.11110645
Primary Topic: Optical Network Technologies
Type: article
Field-Weighted Citation Impact: 0.00

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article

Block-Wise MLSE Processing with Small Overlap for Digital Coherent Parallel Implementation

Shuto Yamamoto, Etsushi Yamazaki, Hiroki Taniguchi, Y. Nakajima

Jun 29, 2025

Optical Network Technologies

article

Block-Wise MLSE Processing with Small Overlap for Digital Coherent Parallel Implementation

Shuto Yamamoto, Etsushi Yamazaki, Hiroki Taniguchi, Y. Nakajima

June 29, 2025article en

Abstract

NTT (Japan) (JP)

Openalex Percentile: Top 80%

Optical Network Technologies

DOI Source OpenAlex

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Block-Wise MLSE Processing with Small Overlap for Digital Coherent Parallel Implementation — Shuto Yamamoto, Etsushi Yamazaki, et al. · (2025) | TGRS Research Map | TGRS