Integrated Testing Strategy of Wafer and Chip-Level Characterization for Photonic Integrated Circuits
We demonstrate wafer-level characterization of both passive silicon photonic integrated circuits and heterogeneously integrated III-V membrane DFB lasers on silicon. Strong agreement with chip-level results enables efficient screening tests for heterogeneous photonic integration.
Authors
- Nobuhiko Nishiyama (ORCID: https://orcid.org/0000-0001-8288-6690)
- Suguru Yoshida (ORCID: https://orcid.org/0000-0001-5888-9330)
- Moataz Eissa (ORCID: https://orcid.org/0000-0002-4339-2724)
- Tsuyoshi Horikawa
Institutions
- Tokyo Institute of Technology (JP)
Publication Details
- Published
- 2025-06-29
- DOI
- https://doi.org/10.23919/oecc/psc62146.2025.11109358
- Primary Topic
- Integrated Circuits and Semiconductor Failure Analysis
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- New Energy and Industrial Technology Development Organization