Low Parasitic Loop Inductance Design and Characterization of a 1200 V, 200 A SiC MOSFET Half-Bridge PCB-embedded Power Module
In this article, the design and characterization of a 1200 V, 200 A rated printed circuit board (PCB) embedded silicon carbide (SiC) MOSFET half-bridge is being presented. The layout of the power module has been optimized to reduce the power loop inductance, achieving a 1.5 nH of power loop inductance. The dimensions of the fabricated module are 48 mm x 32 mm (L x B), with the thickness being 0.35 mm, leading to a reduction of 57% in footprint and a reduction of 95% in volume compared to commercially available half-bridge SiC MOSFET power modules of 1200 V, 200 A with the GM4 package.
Authors
- Aditya Bhalotia
- A. Chaudhary (ORCID: https://orcid.org/0009-0000-2635-3718)
- Mike Morianz
- K Gopikrishnan
- Gerald Weis
- Sumit Pramanick (ORCID: https://orcid.org/0000-0002-7797-2145)
- Johannes Stahr
- Kaushik Mirdoddi (ORCID: https://orcid.org/0009-0009-1961-6319)
- Anandarup Das (ORCID: https://orcid.org/0000-0001-5326-9570)
- Soumya Shubhra Nag (ORCID: https://orcid.org/0000-0003-1043-2934)
- Thomas Koeck
- Sorra Ranjit
Institutions
- Indian Institute of Technology Delhi (IN)
Publication Details
- Published
- 2025-06-22
- DOI
- https://doi.org/10.1109/compel57166.2025.11121202
- Citations
- 1
- Primary Topic
- Silicon Carbide Semiconductor Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.73