Optimization and Impact of Gate Stack on 22 nm Triple Gate FinFET Architecture for Enhanced Electrical Performance

This paper proposes four Triple Gate (TG) FinFET architectures (D1, D2, D3, and D4) on SOI substrate, with fin height and fin width variations and a gate length of 22 nm. The aim is to analyze fin dimensions impact on DC properties of FinFET and to produce an optimal device. In terms of Ioff, capacitances, Ion/Ioff, and SS, the D4 device is found to be the best. Furthermore, D4 device is utilized to investigate the impact of high-k dielectrics in gate stacking. Al<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> and $\mathrm{Si}_{3} \mathrm{~N}_{4}$ were chosen as high-k dielectric in stack with SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>. $\mathrm{S} 1, \mathrm{~S} 2$, and S 3 samples are a combination of SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>, $\mathrm{SiO}_{2}+\mathrm{Si}_{3} \mathrm{~N}_{4}$, and $\mathrm{SiO}_{2}+\mathrm{Al}_{2} \mathrm{O}_{3}$ respectively with an equivalent oxide thickness of 1 nm. S3 sample outperforms the other two samples in terms of DC parameters. S3 sample has lower subthreshold swing (SS) of $53.1 \mathrm{mV} /$ decade and better Ion/Ioff of an order of approximately $10^{8}$. Hence, the S3 sample is best suited for low-power circuits.