A RISC-V Approach to Energy-Efficient Cryptographic Processing in IoT Application

This paper discusses a hardware accelerator designed using the RISC-V architecture, optimized for SHA-256 cryptographic hashing in Internet of Things (IoT) and edge computing environments. As IoT device usage grows, efficient and secure solutions are crucial due to limited computational resources.The accelerator reduces the number of instructions for SHA-256 computation by about 46%, enhancing processing times for applications requiring real-time responses. Its compact design is ideal for space-constrained devices, utilizing optimized data paths and pipelining to improve throughput and lower latency.By accelerating cryptographic operations, the accelerator addresses IoT security concerns, ensuring data integrity and confidentiality, which are vital for user trust. The open RISC-V architecture allows for customization, enabling developers to meet specific security and efficiency needs within the IoT ecosystem. Overall, this work presents a significant advancement in developing secure and efficient cryptographic solutions for IoT devices.