Simulation of Temperature Distribution in Large-Area Joints in Power Electronics

This paper deals with a simulation of temperature distribution in large-area joints used in power electronics modules. The simulation models were created using Solid Edge software. Each simulation model contained a SnAg solder foil with different proportions of voids. That was used between the DBC substrate and the baseplate. At the end of each simulation, the maximum junction temperature on the silicon chip and temperature on the underside of the baseplate was measured. The thermal resistance between a silicon chip and the underside of the baseplate was calculated from the measured data. The results showed that with a higher proportion of voids in the solder, the junction temperature and thermal resistance increased nonlinearly under the same simulation conditions.