A 3–5.5 GHz Compact, Power-Efficient, Switched LC Delay-Line With 0.2–1.1 ns Delay Range

This work presents a single-ended, linear-periodically time-varying (LPTV), two-port, inductor–capacitor (LC) delay-line offering broadband programmable delay of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.2\!-\!1.1\,\mathrm{ns}$</tex-math> </inline-formula> between 3 and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.5\,\mathrm{GHz}$</tex-math> </inline-formula> in a 65-nm bulk CMOS technology. The architecture is based on stitching together the harmonic peaks of an eight-path filter spaced at multiples of the clocking frequency. Shunting one inductor at each of the radio frequency (RF) ports broadens the skirts of the harmonic bands to form the wide passband of the delay-line. The inductors are used to increase the bandwidth of signal acquisition and not as memory. This minimizes the passband loss due to on-chip inductors. The resulting compact single-ended delay-line has a delay–bandwidth product (DBW) of 2.75 and DBW per unit area of 8.46/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {mm}^{2}$</tex-math> </inline-formula>. Thanks to the all-passive nature, the chip dissipates less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\,\mathrm{mW}$</tex-math> </inline-formula> of clocking power and has a P1dB of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$+2\,\mathrm{dBm}$</tex-math> </inline-formula>. The measured in-band loss and noise figure (NF), which are dominated by the on-resistance of the switches, are <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$15\,\mathrm{dB}$</tex-math> </inline-formula> each. A theoretical framework to analyze N-path delay-lines with a memory element attached to the common node between the N-paths has also been presented. The analytical solutions show close agreement with the simulated and the measured results. In terms of the DBW/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {mm}^{2}$</tex-math> </inline-formula>, the architecture is small enough to be compared to active delay-lines, whereas, in terms of insertion loss (IL) and linearity, its performance is better than all-passive delay-lines.