A High-Area-Efficiency Computing-in-Memory Deep Learning Accelerator Based on Weight-Sparsity Activation Compression and Sparsity Reciprocity

The large number of parameters in DNNs poses significant challenges for resource-constrained hardware. To address this, researchers have focused on model sparsity to skip redundant computations and improve inference speed and computing-in-memory (CIM) techniques to reduce data transfer delays and lower energy consumption. However, leveraging activation sparsity within CIM macros remains challenging due to its architectural limitations, leading to bottlenecks in this research direction. This study proposes a activation compression method based on the CIM structure and weight sparsity, along with a new approach called sparse reciprocity, to enhance model sparsity. A high-area-efficiency CIM-based accelerator chip was developed using these techniques and prior expertise. Experiments on various models and data precisions demonstrate a activation compression ratio of up to 54%, with the proposed accelerator achieving an area efficiency of 243 GOPS/mm² for the VGG16 model and 363 GOPS/mm² for the ResNet18 model.