Self-Limited Ti Silicide Contact at 350 °C for Dual-Side Wafer-Level Integration

As integrated circuits advance toward dual-side wafer-level integration, thermal budget constrained contact process has emerged as a critical bottleneck for post back-end-of-line (BEOL) integration. This work introduces a thermally sustainable contact technology utilizing self-limited Ti silicide formed at 350 °C, representing the lowest thermal budget ever reported for Ti silicide-based contact. By employing a revised ladder-based transmission line method, we extracted the ultra-low contact resistivities of 1.63×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> Ω·cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 4.23×10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> Ω·cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> for n- and p-type source/drain at 350 °C, respectively. Benefiting from the self-limiting reaction mechanism, this approach enables precise silicidation control under ultra-low thermal budget, demonstrating full compatibility with backside thermal stability requirements (<400 °C). This development may facilitate the backside device and interconnect integration while preserving the integrity of front-side processes, making a key step toward the dual-side 3D integration.