A Fully-Integrated Adaptive Bias Circuit for DCR Regulation in Single-Photon Avalanche Diode Arrays

The breakdown voltage (VBD) of each single-photon avalanche diode (SPAD) in a large array typically varies due to process variations, leading to variations in excess bias voltage (VEX) and detection performance of SPADs across the array. In this letter, a fully-integrated adaptive bias circuit for dark count rate (DCR) regulation in SPADs is proposed, where DCR is utilized as a uniformity indicator of different SPADs, and a counter with an adjustable time window is employed to obtain the DCR of each SPAD, and DCR regulation is performed via programmable compensation current connected to the anode of each SPAD to ensure similar DCR of all SPADs. Fabricated in a standard 180 nm CMOS process, the proposed adaptive bias circuit achieves a voltage tuning range of 460 mV, which suppresses DCR variation ratio (maximum DCR / minimum DCR) from 15.2 to 4.1 among four SPADs in a macro-pixel for a target DCR of 2 kHz.