A High‐Speed Simultaneous Wireless Power and Multibit Data Transfer System

ABSTRACT Existing single‐channel simultaneous wireless power and data transfer (SWPDT) systems are fundamentally constrained by their single‐bit transfer architecture, which seriously restricts the achievable data rate. To address these limitations, this paper proposes a simultaneous wireless power and high‐speed multibit data transfer (SWPHMDT) system. To achieve high‐speed data transmission, a multichannel parallel data transmission architecture is proposed, with a secondary‐side demodulation method based on transient response. By utilizing a multifrequency blocking network, the system effectively isolates data channels from the power channel, ensuring reliable power transfer. The system architecture and operational principles of the SWPHMDT system are described in detail. A dual‐channel SWPHMDT configuration is developed based on a four‐resonance dual‐reflective (FRDR) structure, with analytically derived operating conditions. The crosstalk mechanisms between channels are investigated, and the parametric dependencies of system performance are examined. Furthermore, the optimal regulation resistance for high‐speed data transmission is derived based on the transient response characteristics of the data channels. Experimental validation is carried out using a 356.07‐W prototype, demonstrating a 2‐Mbps data rate, 86.483% power transfer efficiency, and a data transfer delay of 1.8 μs.