MPD - Multi-Project Die Sharing Enabled by an Embedded FPGA

The cost for taping out chips in older (mature) technology nodes has decreased significantly in recent years and, for instance, multi-project wafer MPD runs in 130 nm are now available below USD 10 K. In this paper, we will use an embedded FPGA (eFPGA) for integrating multiple smaller user designs into a shared die, called multi-project die - MPD for further reducing cost. This will be possible by sharing an MPW die among multiple users. For instance, in our case study, 7 user designs are sharing one 130 nm MPW run, which allows a tapeout run well at around <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1 ~\mathrm{K}-2 ~\mathrm{K}$</tex> USD. The eFPGA is not only used for integrating user designs and connecting them to some shared I/O pins, it can also provide useful features for operating and debugging of user designs, such as providing memories, trace buffers or time-to-digital converters. The system presented here will exceed the capabilities of a previous infrastructure that had been provided to make (single user) chip design accessible to a wider community.