Efficient DSP Packing Method for Neural Network Accelerator

FPGA accelerators for convolutional neural networks (CNNs) have made significant progress in recent years. It is critical to fully utilize scarce digital signal processor (DSP) resources on FPGAs to implement CNNs dense multiply-and-accumulate (MAC) operations. Many works pack multiple parallel multiplications into a single DSP to improve the efficiency and performance of the DSP. However, these works usually pack two or four multiplications into the DSP, or use approximate computation to boost packing density at the expense of accuracy. In addition, neglecting the resource consumption of the packing and unpacking process leads to an increase in hardware area. To address these issues, this paper implements a single DSP packing six signed multiplications for lossless computation. Moreover, the resource consumption of the data packing and unpacking process is analyzed and optimized for the first time, which leads to a 48.7% decrease in look-up tables (LUTs) resource utilization. Compared to the state-of-the-art accelerator design, our system design achieves <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$2.03 \times$</tex> throughput with almost the same resource consumption and lower energy efficiency.