CGRA-HD: An Efficient Reconfigurable Accelerator for Hyperdimensional Computing: (PhD Forum Paper)

Hyperdimensional Computing (HDC), which leverages the distributed computational characteristics of hypervectors, is gaining significant attention due to its outstanding classification performance and hardware friendliness. However, the coarse-grained computational characteristics in HDC are largely unexplored. To this end, we present CGRA-HD, a coarse-grained reconfigurable architecture (CGRA) for accelerating the HDC algorithm. By analyzing the frequent operations and general sub-graphs, we explore the specialized Processing Element (PE) design for HDC to realize efficient acceleration. The specialized PE and the general one constitute a CGRA-HD array and have been integrated into a state-of-the-art RISC-V+CGRA SoC. Our evaluation shows that CGRA-HD greatly improves HDC performance over CPUs with decreased area and power consumption compared to the general CGRA.