GraphNoC: Graph Neural Networks for Application-Specific FPGA NoC Performance Prediction

We can democratize design of FPGA Network-on-Chips by replacing slow and expensive conventional NoC benchmarking tools with highly accurate and fast Graph Neural Networks based models. FPGA reconfigurability allows for tuning and designing of NoCs specific to the application being implemented on the FPGA, a facility not afforded to ASIC NoCs. However, such application-specific NoC designs can require thousands of incremental updates and customization to the NoC design, with each resulting NoC configuration needing benchmarking for packet performance to guide the design process. Additionally, each of these benchmark runs can take up to minutes with conventional tools like RTL simulation for modest packet trace lengths. As a result, tuning and design of a NoC even for a single FPGA application can last up to days, presenting a critical bottleneck to developer efficiency and iteration speed. We address this by presenting a framework to encode any FPGA NoC and any FPGA application traffic into graphs, called GraphNoC. We create a dataset of these graphs, comprising of different FPGA NoCs and applications. We use this dataset to train GNNs, including foundation models, to predict NoC routing latencies that can accelerate benchmarking run-times by up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$148 \times(506 \times$</tex> using GPU) with prediction top-20 accuracies up to 97.2 %. We also show these GNNs can accelerate end-to-end FPGA application-specific NoC design by up to <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$4.3 \times$</tex> (<tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$37 \times$</tex> using GPU) while regressing final NoC latency by only 30 cycles.