A 2–18-GHz Reconfigurable Phased-Array Receiver Front-End in 65-nm CMOS
This article presents an ultra-wideband reconfigurable phased array receiver (RX) front-end covering the 2–18 GHz band. To fix the tradeoff between bandwidth (BW), gain, phase root mean square (RMS) error and gain rms error performance, we introduce a fully-reconfigurable technology for the phase-array received front-end, including: 1) reconfigurable phase shifter (PS) with reconfigurable resistor-capacitor (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i>)-resistor-inductor (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RL</i>)-<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> polyphase filter (PPF) <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i>/<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> generator, which is capable of realizing dual-band switching and reducing the gain-phase error and 2) reconfigurable low-noise amplifier (LNA), based on a reconfigurable feedback network (RCFN) and a reconfigurable load network (RCLN), ensuring a consistently low and flat noise figure (NF) along with an extended gain BW across the entire operating band. The RX also encompasses a wideband attenuator (ATT), active baluns, and driving amplifier (DA), each of which exerts a negligible influence on the overall system performance and is wideband-designed to simplify the design process and ease implementation. The phased-array RX is manufactured by TSMC 65-nm CMOS technology. Measurement results show that the proposed RX achieves an NF of 2.6–4 dB and a rms phase error of 0.4°–3.3° in the 2–18 GHz band. The input 1 dB compression point (IP<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${}_{\text {1 dB}}$</tex-math> </inline-formula>) is −29.6 to −26.7 dBm at 132 mW power consumption.
Authors
- Yuanan Liu (ORCID: https://orcid.org/0000-0002-8076-1904)
- Tao Yang (ORCID: https://orcid.org/0000-0001-7459-6052)
- Jianbin Liu (ORCID: https://orcid.org/0000-0001-9712-2722)
- Shuangyang Wu (ORCID: https://orcid.org/0000-0001-6305-3204)
- Zhihua Wei (ORCID: https://orcid.org/0000-0002-1216-5537)
- Pei‐Ling Chi (ORCID: https://orcid.org/0000-0001-9515-4317)
Institutions
- Beijing University of Posts and Telecommunications (CN)
- National Yang Ming Chiao Tung University (TW)
- University of Electronic Science and Technology of China (CN)
Publication Details
- Journal
- IEEE Transactions on Microwave Theory and Techniques
- Published
- 2025-08-18
- DOI
- https://doi.org/10.1109/tmtt.2025.3596492
- Citations
- 1
- Primary Topic
- Radio Frequency Integrated Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.73
Funders
- National Natural Science Foundation of China