A Low-Jitter and Spur Dual-Edge Sub-Sampling Phase-Locked Loop With Double-Balanced Sampling Mixer-Adopted Phase Detector

Advancements in high-speed wireline and wireless applications are driving the demand for high-performance frequency synthesizers. The conventional sub-sampling phase detector (SSPD) suffers from poor reference spur performance, limiting the overall effectiveness of the sub-sampling phase-locked loop (SSPLL). This article presents a SSPLL incorporating a double-balanced sampling mixer-adopted SSPD (DBSMA-SSPD). The proposed design improves the reference spur by reducing reference feedthrough without requiring external calibration or RC networks. A dual-edge sampling technique is introduced to further enhance in-band phase noise performance. The proposed SSPLL employs an LC-voltage controlled oscillator (VCO) as its core to generate a 2.688 GHz frequency. The design is implemented and fabricated using an industrial 65-nm CMOS process, occupying a total active area of 0.39 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. The SSPLL successfully locks to a 2.688 GHz frequency from a reference frequency of 168 MHz, consuming around 4.1 mW from a 1.2-V supply. The design demonstrates state-of-the-art performance, achieving a measured rms jitter of 207.7 fs over an integration bandwidth of 10 kHz–100 MHz and a measured reference spur of −72 dBc, attributed to the proposed DBSMA-SSPD. Additionally, it achieves an in-band phase noise of −122.16 dBc/Hz at a 200-kHz frequency offset, with a jitter-power figure-of-merit (FOM) of −247.5 dB.