A Novel Readout Scheme With Controllable Delay Chains for High-Precision Time Resolution in Pixel Detectors

With the increasing deployment of pixel detectors in particle physics, imaging systems, and other high-precision applications, improving time resolution and signal processing speed has become a pressing challenge. Traditional readout schemes often struggle with the trade-off between accuracy and efficiency. This study proposes a novel readout architecture that incorporates controllable delay chains to facilitate multi-directional signal propagation, enabling precise event localization through transmission path differences. Each pixel circuit integrates a low-noise charge-sensitive amplifier, a comparator, and a tunable delay unit, collectively enhancing signal fidelity and timing accuracy. Fabricated using the TSMC 180 nm CMOS process, two configurations are implemented: a four-directional delay chain (ASIC-I) and a two-directional variant (ASIC-II), tailored to varying signal propagation needs. Experimental results demonstrate that the ASIC-I chip, configured as a 3 × 3 pixel array, achieves a per-pixel time resolution of 52.8 ps. The delay unit provides 7 adjustable levels with a range from 2.27 ns to 15.55 ns. The measured system time precision (RMS jitter) is 160 ps. Reliability tests under varying process, voltage, and temperature (PVT) conditions show robust performance, with a temperature coefficient ranging from 7 ps/°C to 44 ps/°C. These results validate the proposed scheme’s feasibility and robustness, offering promising potential for high-speed, high-resolution particle detection and real-time data acquisition systems.