Fracture dynamics in Smart Cut™ technology: Wafer deformation measurement

• Solar cell implemented with PIN diode controlling the depletion region by a MOS capacitor placed over its intrinsic region (substrate). • Solar cell implemented with two different layout styles (rectangular and half-circular). • Solar cell implemented with half-circular layout style and PIN diode is an alternative to improve its electrical performance. High-Speed Cameras help in characterizing the splitting step in the Smart Cut™ technology. Full wafer-scale deformation monitoring upon annealing is then possible. This paper describes the setup, equipment and methodology used to estimate the backside wafer deformation and curvature upon fracture propagation in situ during the fracture step. Finally, with such a setup, the fracture process of a SOI-ready structure is studied dynamically over the whole propagation time scale. These results are consistent with literature work performed using punctual measurements methods and will allow in the future to emphasize the effect of process’ and structure’s geometry.

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Publication Details

Journal
Solid-State Electronics
Published
2025-08-18
DOI
https://doi.org/10.1016/j.sse.2025.109218
Primary Topic
Advanced Surface Polishing Techniques
Type
article
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article

Fracture dynamics in Smart Cut™ technology: Wafer deformation measurement

F. Rieutord, Lucas Colonel, Didier Landru, Kevin Blanco et al.
Solid-State Electronics
Advanced Surface Polishing Techniques
article

Fracture dynamics in Smart Cut™ technology: Wafer deformation measurement

F. Rieutord, Lucas Colonel, Didier Landru, Kevin Blanco, Samuel Tardif, F. Mazen, J. Eymery, Pablo Eduardo ACOSTA ALBA
article en

Abstract

• Solar cell implemented with PIN diode controlling the depletion region by a MOS capacitor placed over its intrinsic region (substrate). • Solar cell implemented with two different layout styles (rectangular and half-circular). • Solar cell implemented with half-circular layout style and PIN diode is an alternative to improve its electrical performance. High-Speed Cameras help in characterizing the splitting step in the Smart Cut™ technology. Full wafer-scale deformation monitoring upon annealing is then possible. This paper describes the setup, equipment and methodology used to estimate the backside wafer deformation and curvature upon fracture propagation in situ during the fracture step. Finally, with such a setup, the fracture process of a SOI-ready structure is studied dynamically over the whole propagation time scale. These results are consistent with literature work performed using punctual measurements methods and will allow in the future to emphasize the effect of process’ and structure’s geometry.

Solid-State ElectronicsVol. 229
Soitec (France) (FR), Commissariat à l'Énergie Atomique et aux Énergies Alternatives (FR), CEA Grenoble (FR), Laboratoire d'Électronique des Technologies de l'Information (FR), Université Grenoble Alpes (FR)
Openalex Percentile: Top 80%
Advanced Surface Polishing Techniques
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Fracture dynamics in Smart Cut™ technology: Wafer deformation measurement — F. Rieutord, Lucas Colonel, et al. · Solid-State Electronics (2025) | TGRS Research Map | TGRS