Soft Error Analysis in NSFET and FSFET: From Device Physics to Circuit and Memory Impact

We investigate the Single Event Upset (SEU) reliability of Nanosheet Field-Effect Transistors (NSFETs) and Forksheet Field-Effect Transistors (FSFETs). Calibrated TCAD and BSIM compact models are used to assess Heavy-Ion Radiation (HIR) impact from device to circuit level. First, we investigate the impact of HIR on the device characteristics in TCAD and reveal that due to higher recombination rates, the collected charge for FSFET is lower than NSFET. Peak current and collection time for FSFET are also lower for all Linear Energy Transfer (LET) and V DD , hence achieving a better bipolar gain (β). At circuit level, the comparison is based on metrics including masking efficiency (η), critical LET (LET Crit), and Soft Error Rate (SER) for inverter chains, D Flip-Flops (DFFs), and Static Random-Access Memories (SRAMs). The FSFET achieves η ≥ 0.60, and shows masking higher than the NSFET. The logic LET Crit at 0.70 V, improves by 34.80%, and the probability of error-latching by 33% with FSFET. At 0.70 V, SRAM LET Crit with NSFET is 18.36% worse than the FSFET. Next, we compare SER for HIR exposure: (1) at sea-level, (2) in Geosynchronous/Geostationary orbits, and (3) for a solar-flare event. FSFET logic outperforms NSFET, with a 52% lower SER at the sea-level. For memory circuits, the improvement is 8.81%. The SEU susceptibility of FSFET increases for oblique and transverse strikes due to the compact n-/p-FET packing, highlighting the need for appropriate radiation hardened circuit design.