Estimating FPGA-Based Terahertz Transmitter Chain Performance For Live Data Flow

Terahertz wireless communication researchers are increasingly adopting field-programmable-gate-arrays (FPGA) with RF Systems on Chip (RFSoC) to realize critical elements of the transmit and receive chains. Even with latest generation hardware, achieving truly live data flow >1 Gbps remains a significant challenge. Speed limitations within the digital signal processing (DSP) hardware internal to the FPGA limit data exchange with external application layers. For this reason, extant work often uses random data generated within the FPGA to bypass this challenge while still demonstrating the performance of the physical layer. In this work, we implement a single RF channel, FPGA-based transmitter chain that demonstrates live data flow at 768 Mbps, including every layer of the network stack except final upconversion. We use these results to identify the data rate bottlenecks in our implementation and provide informed extrapolations on the limits of transmitter chain performance using the full capabilities of state-of-the-art FGPA hardware.