A Comprehensive Evaluation of Side-Channel Resistance of <scp>Xoodyak</scp> Hardware Implementations

In this paper, we conduct an in-depth power side-channel analysis of Xoodyak, a lightweight cryptographic algorithm implemented on an FPGA platform. Our analysis focuses on the initialization phase of Xoodyak in its authenticated encryption with associated data mode. We introduce a new leakage model and perform an initial leakage assessment to identify potential vulnerabilities. Subsequently, we carry out both non-profiled and profiled attacks to determine how exploitable the observed leakages are. We use correlation power analysis for the non-profiled analysis, applying it across all key bits. This approach yields a success rate of 91.4% with 50,000 traces. In our profiled attack phase, we deploy both a template attack and a deep learning-based attack. The template attack achieves a success rate of 99.2%, recovering almost all key bits using 20,000 traces. Meanwhile, the deep learning approach reaches zero guessing entropy within 550 traces and successfully adapts to the leakage model within 50 epochs. To enhance the resilience of Xoodyak against side-channel attacks, we develop a configurable implementation based on domain-oriented masking (DOM) scheme. Our d-th order masked implementation employs [Formula: see text] shares, requiring [Formula: see text] units of fresh randomness per round. We then assess the resource requirements of these masked implementations on both ASIC and FPGA platforms, up to order 5. As a practical demonstration, we program the main Spartan-6 FPGA on the Sakura-G evaluation board with both the unprotected and the first-order domain-oriented protected implementations. A test vector leakage assessment based on Welch’s t-test is then conducted to confirm the improved resistance of this Xoodyak implementation protected against first-order power analysis attacks.