The ESD Robustness of Schottky-Gate <i>p</i>-GaN HEMT Under Different States

This work systematically investigates the electrostatic discharge (ESD) robustness of Schottky-gate p-GaN high electron mobility transistors (HEMTs) under different gate and drain bias conditions. Gate-terminal ESD robustness is severely compromised under high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}}$ </tex-math></inline-formula> (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\ge 40$ </tex-math></inline-formula> V), where synergistic high voltage/current induces thermal runaway, causing irreversible damage. At <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {DS}} =5$ </tex-math></inline-formula>–30 V, trap-dominated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shifts (up to 0.68 V) correlate with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1200\times {N}_{\text {it0}}$ </tex-math></inline-formula> increases, partially recoverable over time. With the drain in the floating state, the trap-dominated <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {TH}}$ </tex-math></inline-formula> shift (about 0.47 V) correlate with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$140\times {N}_{\text {it}}$ </tex-math></inline-formula> increases, nearly fully recoverable over time. Under the drain-terminal ESD events, the device with the gate in floating state exhibits superior ESD robustness, accompanied by only a 0.12-V negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{\text {TH}}$ </tex-math></inline-formula> shift and high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {HBM}}$ </tex-math></inline-formula> of over 8.61 kV. The devices with gate biased at off/semi-on/on states achieve <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {HBM}}$ </tex-math></inline-formula> from 0.27 to 30 kV, with (semi-on) on-state configurations meeting 2-kV industrial standards. This work bridges the gap in understanding multistress ESD interactions, providing critical insights for optimizing p-GaN HEMT reliability.