A Modified 1/ f Noise Model for Narrow-Width Si p-MOSFETs With Shallow Trench Isolation

In this work, a modified low-frequency (1/f) noise model is proposed for the narrow-width Si p-MOSFETs with the shallow trench isolation (STI) structure for the first time. It is found that the normalized drain current noise power spectral density (PSD) (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${S} _{\textit {Id}}$ </tex-math></inline-formula>/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I} _{d}^{{2}}$ </tex-math></inline-formula>) of p-MOSFETs initially increases before sharply decreasing as the channel width (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W} _{g}$ </tex-math></inline-formula>) decreases, which does not agree with the predictions of the unified 1/f noise theory (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\Delta } {N}$ </tex-math></inline-formula>–<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \mu $ </tex-math></inline-formula> model) in MOSFETs. This phenomenon indicates that the inverse-narrow-width effects (INWEs) can suppress the 1/f noise of drain current for narrow-width p-MOSFETs with STI due to the enhanced carrier density at the edge width (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W} _{e}$ </tex-math></inline-formula>). Furthermore, a simple quantitative model is introduced to well predict the impact of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W} _{e}$ </tex-math></inline-formula> on 1/f noise and estimate the channel width at which p-MOSFETs with STI exhibit the worst 1/f noise performance. And the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${W} _{e}$ </tex-math></inline-formula> for Si p-MOSFET at 55-nm node derived from this model is consistent with the reported value of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.05~\mu $ </tex-math></inline-formula>m extracted by the parasitical series resistance (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R} _{{p}{0}}$ </tex-math></inline-formula>) method, thereby effectively validating the proposed 1/f noise model. These results provide valuable insights into understanding and optimizing the 1/f noise behavior of narrow-width devices with STI in future advanced technology nodes.