High efficiency hardware implementation of a ZP-OTFS modulator for next generation high-mobility wireless systems

Orthogonal Time Frequency Space (OTFS) is an emerging transmission technology poised to become the dominant paradigm in High-mobility wireless communications and a potential successor to the current Orthogonal Frequency Division Multiplexing (OFDM) technology. In this article, we propose a Zero Padded OTFS (ZP-OTFS) modulator that incorporates the logic required for pilot insertion, zero padding, cyclic prefix, and payload data management. Additionally, the Register Transfer Level (RTL) architecture on Field-Programmable Gate Arrays (FPGAs) and Application-Specific Integrated Circuits (ASIC) will be discussed, with particular focus on the first one. A comparison with state-of-the-art architectures is also conducted to evaluate its performance. The implementation results demonstrate that the proposed architecture offers significant advantages in terms of resource utilization, achieving an improvement percentage up to about 90%, being capable of attaining clock frequencies up to over 600 MHz while maintaining low power consumption. Furthermore, our study explores the relationship between latency, dynamic power consumption, and resource utilization as functions of frame size, proposing design parameters that account for both transmission channel characteristics and hardware constraints, allowing the development of a real OTFS-based transceiver system. Finally, a complete transmission system is presented by integrating the proposed modulator into a complete transmission chain. The transmitted signal is analyzed to validate the effectiveness of the proposed approach. • VLSI ZP-OTFS modulator for high-mobility systems with embedded pilot design. • Detailed RTL architecture on Field-Programmable Gate Arrays (FPGAs) is discussed. • Comparison with state-of-the-art architectures is conducted to evaluate performance. • Full FPGA-based transmission validated on ZCU111 RFSoC with 16 Gbps output.