SIRENA: SparsIty-REpetition aware Nibble-based hardware Accelerator for convolutional neural networks

The growing demand for artificial intelligence (AI) applications demands specialized hardware accelerators to handle intensive computational loads. To reduce computing needs, this paper introduces nibble decomposition (NBD), a method that splits 8-bit values into two 4-bit nibbles to detect and remove redundant computations in convolutional neural networks (CNNs). Experiments with INT8 quantized ResNet-50, MobileNet, and YOLO-V3 show that nibble decomposition can avoid up to 91% of multiplications in the upper nibble and 70% in the lower nibble. We further propose SIRENA, an NBD hardware accelerator to optimize 8-bit quantized CNNs by skipping redundant operations without accuracy loss. Building on this method, we present SIRENA, an NBD-based accelerator that skips redundant operations without accuracy loss. Compared to a conventional value-agnostic accelerator, SIRENA achieves a 55% reduction in power consumption. • NBD reduces up to 91%/70% of MACs for the most/least significant nibbles. • NBD can be used with quantization and sparsity without extra accuracy loss. • SIRENA accelerator skips redundant ops in 8-bit quantized CNN layers. • SIRENA presents a 55% power reduction compared to a value-agnostic HW accelerator.