Design of a Highly Stable and Robust 9T SRAM Cell Using CNTFET for Low Power Smart Device Applications

Constructing an SRAM (Static Random Access Memory) cell significantly impacts speed, area, stability and power consumption. This study proposes a stable and all-round SRAM cell utilizing nine transistors (9T) constructed with Carbon Nano Tube Field Effect Transistors (CNTFETs) which integrates a noise-tolerable Schmitt Trigger (ST) circuit and dynamic body biasing within its core. To boost performance, it incorporates feedback-cutting method and read disturbance decoupling for enhancing WSNM and RSNM respectively. The proposed cell utilizes a single bit-line for both write and read operations. The write power, read power, hold power, RSNM, HSNM, WSNM, write delay and read delay of the proposed 9T CNTFET SRAM cell are 1.5811 nW, 3.0801 nW, 1.5823 nW, 374.8 mV, 374.8 mV, 430.0 mV, 40 pS and 78.914 pS respectively. Performance analysis has also been conducted to assess the proposed cell's performance and for simulation a standard CNTFET library by Stanford university is used to analyze its characteristics in 32nm technology.