Simulation-Based Performance Evaluation of Telescopic Op-Amps in SCL 180nm, GPDK 180nm, and GPDK 45nm CMOS Technologies

This paper presents a comparative simulation-based analysis of a telescopic operational amplifier (op-amp) implemented across three CMOS technology nodes: SCL 180nm, GPDK 180nm, and GPDK 45nm. However, detailed transistor-level sizing, biasing, and compensation techniques were explored to assess the effect of technology scaling on key analog performance parameters. Using Cadence Virtuoso, gain, phase margin, unity gain frequency (UGF), and power dissipation were extracted for each process. Results reveal that the GPDK 45nm design achieves the lowest power consumption (0.56 mW) with acceptable stability and speed, while the SCL 180nm variant offers high gain but at higher power cost. This work highlights how simulation-driven optimization and technology-aware design adjustments can be leveraged to fine-tune analog circuit performance across different process nodes.