A Comprehensive Modeling of Gate Stack Interlayer Engineering for Ferroelectric Vertical NAND

Ferroelectric field-effect transistors (FeFETs)-based vertical NAND (Fe-VNAND) has emerged as a promising solution to z-scaling limitations of conventional charge trap layer (CTL)-based VNAND (Fig. 1) with reduced programming voltage (from $\gt30 \mathrm{~V}$ to $(\lt)15 \mathrm{~V}$) [1]. Band engineered FeFETs are actively being explored to enable multilevel (3-bit per cell) operations [2, 3]. Although the gate blocking layer (GBL) allows higher memory window (MW>7 V) [4], it suffers from poor retention characteristics [5] which lead to more sophisticated gate stack engineering by inserting Al<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> tunnel dielectric layer (TDL) in the middle of FE stacks (Hf<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</inf>Zr<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>(HZO)) to achieve high MW and robust retention (Fig. 2) [4 –6]. In this paper, a comprehensive TCAD-based analysis of interlayer gate stack engineering is performed to understand time-dependent interplay between charge trapping and polarization, as well as the impact of ferroelectric/dielectric phase variations. This dynamic modeling approach is crucial for guiding effective gate stack design in Fe-VNAND applications.