HGPplace: Hierarchical Chip Layout Optimization Combining Graph Convolutional Networks and Polygon-Aware Placement

Since the advent of Electronic Design Automation (EDA) in integrated circuit (IC) design, layout optimization has become a critical factor in determining chip performance, power consumption, and area utilization (PPA). Current layout methods for digital circuits predominantly employ flat one-shot placement strategies, while analog netlists with hierarchical descriptions often simplify subcircuits into rectangular modules. These approaches neglect the actual geometric shapes of components, leading to suboptimal space utilization and performance limitations. This paper proposes a novel layout optimization framework HGPplace addressing these challenges through two key innovations: 1) A graph convolutional reinforcement learning strategy that models device connectivity and type similarity using Graph Convolutional Networks (GCNs), optimized via reinforcement learning (RL) to build a topology-aware decision system; 2) A hierarchical layout with polygon-based placement strategy that enables design reuse and maximizes blank space utilization through true geometric modeling. Experimental results demonstrate 20.29%-35.43% improvement in area utilization and 72%-82% improvement in efficiency.