A Data and Clock Recovery Circuit for Gigabit Ethernet

In this paper, a clock and data recovery circuit for Gigabit Ethernet applications is designed. Based on the traditional phase interpolation loop architecture, we introduce an additional quarter-data-rate loop based on the Delay-Locked loop clock chain, which achieves fast clock locking and improves the stability of the system. The circuit was designed and fabricated on a 40nm CMOS process and integrated into a self-developed Tine Sensitive Networking (TSN) chip. The test results indirectly show that the circuit works well in the temperature range of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$-55^{\circ} \mathrm{C} \sim 125^{\circ} \mathrm{C}$</tex>. The data clock recovery circuit performs well and operates normally, with total jitter below 40 ps and Bit Error Rate below <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$10^{-12}$</tex>, which meets the requirements of the Gigabit Ethernet protocol.