Linear variation of threshold voltage with back bias for 22nm FDSOI at cryogenic temperature.

The FDSOI technology has been promising for developing cryo-CMOS IP that is inherent module of qubit read out and control circuit. The FDSOI technology offers us more flexibility of back bias that is evident to control the threshold voltage shift that occurs at cryogenic temperatures. Even though there are several reports on the impact of back bias on the threshold voltage $\left(\mathrm{V}_{\mathrm{TH}}\right)$ at deep cryogenic temperatures<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1–4]</sup>. The exact $\mathrm{V}_{\mathrm{TH}}$ dependency on back bias to develop a model at cryogenic temperatures is not discussed specifically. In particular, the Forward Back Bias (FBB) regime is of great importance for $\mathrm{V}_{\mathrm{TH}}$. The FBB regime is of great interest to Analog IC designers developing cryo-CMOS IP, as $\mathrm{V}_{\mathrm{TH}}$ decreases and high transconductance for better gain and noise reduction in the FBB regime at cryogenic temperatures. In this work, we report the variation of $\mathrm{V}_{\mathrm{TH}}$ with back bias for 22nm FDSOI flipped well super low threshold voltage (SLVT) devices at cryogenic temperature. The flipped well technology gives desirable performance in FBB regime and have lowest $\mathrm{V}_{\mathrm{TH}}$ desired for circuit designers. The devices were measured at 8K and at room temperature (300K) and analysed for VTH behaviour with respect to back bias. The dopant freeze out at cryogenic temperatures in the substrate can lead to significant variations in the effect of back bias.