A Dual-Loop Clock and Data Recovery System with HLD for Extended Lock-in Range Demand

This paper presents a dual-loop Clock and Data Recovery (CDR) circuit designed to retrieve digital data over a range of 0.5 to 5 Gbps. The proposed method for frequency acquisition is founded on a full-rate clock architecture. To enhance the lock-in range, the design incorporates a Hysteresis Lock Detector (HLD), a Frequency Rise/Fall Control circuit, and a Modified Digital Quadri-correlator Frequency Detector (DQFD). The architecture employs two control lines for Coarse and Fine Tuning of the Voltage-Controlled Oscillator (VCO), facilitating distinct loop filters in each of the dual loops, thereby effectively reducing jitter and noise. The circuit has been fabricated using advanced 40-nm CMOS technology, and post-layout simulation outcomes at 5 Gbps demonstrate performance metrics, including a peak-to-peak jitter of 12.7 ps and an RMS jitter of 2.23 ps for the recovered clock signal.