Design of a $12 \times 10$-Gbps VCSEL Array Driving ASIC for High-Bandwidth Communication Links

This paper presents a VCSEL array driving ASIC fabricated in a commercial <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$130-\text{nm}$</tex> SiGe BiCMOS technology. The chip contains 12 independent channels for driving a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1 \times 12$</tex> common-cathode VCSEL array. Each channel consists of an equalizer, a limiting amplifier, and an output driver. The equalizer is designed with sufficient bandwidth to avoid inter-symbol interference and employs a continuous-time linear equalizer structure to compensate for high-frequency attenuation of the input signal on PCB traces. The limiting amplifier further amplifies the signal and is equipped with the function of polarity inversion. Polarity inversion allows the signal to achieve the equivalent of a board-level crossover without additional via impedance discontinuities that degrade the high-frequency integrity of the signal path. The output driver can provide a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5-\text{mA}$</tex> modulation current and a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5-\text{mA}$</tex> bias current for the VCSEL in a typical case. Benefiting from the high-speed performance advantages of the devices in the SiGe BiCMOS process and the innovative and optimized design of the circuit architecture, the channels of the ASIC have achieved an excellent balance between high bandwidth and low power consumption. The measured results of the chip demonstrate that a clean and clear 10 Gbps eye diagram can be obtained under the typical output configuration. The total jitter of each channel is 18 ps, and the power consumption is 47 mW per channel.