A 4A Load Current Ultra-Low Dropout Regulator With Zero Compensation

This paper presents an ultra-low dropout (ULDO) regulator with an innovative zero compensation circuit. The proposed zero compensation circuit, which introduces a lowfrequency zero without modifying the overall circuit architecture or generating additional poles, effectively avoids the reduction in system bandwidth caused by large capacitors while simultaneously minimizing the chip area. By generating the zero on-chip, the proposed design effectively eliminates the transient performance degradation associated with using ESR resistors to introduce zeros. The LDO was fabricated by a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$0.18-\mu \mathrm{m}$</tex> BCD process, with an active area of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$1.46 ~\text{mm} \times 1.88 ~\text{mm}$</tex>. The introduction of zero compensation increases the phase margin by 11.9 deg, ensuring excellent circuit stability. With a load current of 4 A, the dropout voltage is only 55 mV, achieving an ultra-low dropout. Additionally, the design demonstrates an output voltage undershoot of 20 mV at 25° C, along with excellent line regulation and load regulation. The power supply rejection ratio (PSRR) is measured at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{- 6 1 ~ d B}$</tex> at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\mathbf{1 0 ~ k H z}$</tex>.