Enhancing Convolutional Neural Networks With Depth-Aware Architectures: a Systolic Array Approach for Efficient Hardware Implementation

Depth-aware convolution enhances spatial feature extraction in convolutional neural networks (CNNs) but introduces hardware challenges due to dynamic weights and high memory bandwidth requirements. This paper presents a configurable hardware architecture that supports both standard and depth-aware convolution. To address the intensive memory operations, we introduce the Optimal Memory Access Configuration Algorithm (OMACA), which determines variable block sizes for feature maps, depth maps, and weights, thereby reducing external transfers under on-chip cache constraints. Deployed on the AXU15EG development board, our accelerator achieved a 2.18 -fold speed improvement over the CPU, with power consumption only 4.9 % of that of the GPU. Energy efficiency improved by 11.94 times compared to the CPU and 1.63 times compared to the GPU.