Design and Performance Evaluating of Sense Amplifiers for SRAM Cell

With the rapid advancement in the CPU processing power it is necessary to match the pace of the memory section to complement it. The performance of an SOC or embedded system depends on how fast data can be read from memory. The read time of a SRAM (Static Random Access Memory) can be improved by using a sense amplifier which can sense even the smallest of the voltage difference between its two bitlines. In this paper, we have compared various configurations of sense amplifier that can be used in SRAM design. The read time and power consumptions are compared for the various amplifier designs. The simulations for the amplifier designs are done on Cadence Virtuoso at 7nm process technology.