A Feature-Extraction CMOS Image Sensor: Co-Design of On-Chip Processing and Programmable $\pm 3$-Bit $3 \times 3$ Convolution Circuits

This paper proposes a feature-extraction CMOS image sensor (CIS) with column-parallel programmable convolution circuits designed for edge-intelligent sensing. The proposed CIS architecture retains compatibility with conventional 4T pixels without modifications, while enabling correlated double sampling (CDS) to suppress readout noise. Each pixel output in the array will be converted into nine consecutive pulse-width-modulated (PWM) signals for implementing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3 \times 3$</tex> convolution. The proposed convolution circuits implement <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3 \times 3$</tex> convolutions by multiplying <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm 3$</tex>-bit convolutional kernel weights with the PWM signals through current-mirror-based multiplication modules, followed by switched-capacitor accumulation of nine multiplied outputs, thereby executing programmable analog multiply-and-accumulate (MAC) operations at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$\pm 3$</tex>-bit weight precision. Fabricated in 180 nm CMOS, the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$6.88 \mu ~\mathrm{m}$</tex>-pitch convolution circuits demonstrate measured linearity with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$mathrm{R}^{2}=\text{0.97}$</tex>. When employing kernel density estimation (KDE) of circuits non-idealities in a lightweight binary classification convolutional neural network (CNN), the measured results exhibit an 8.2% accuracy degradation compared to ideal convolution.