In-Network Computing Accelerated Risc-V Core for Flexible High-Performance Packet Processing

Data-intensive applications are the cornerstone of today's online services. However, with the gradual slowdown of Moore's law, traditional hardware accelerators are increasingly struggling to meet the performance demands of emerging cloud applications. In this paper, we propose an in-order, partially multi-issued, multi-threaded processor designed to accelerate in-network computing applications. This processor is highly suitable for high-speed and flexible packet data plane processing scenarios. We have extended a set of in-network computingrelated instruction sets, categorizing them based on execution time to reduce the critical path delay. This allows the core to operate at a higher frequency while executing complex instructions. By leveraging blocking multi-threading technology, we effectively hide the overhead of multi-cycle instructions. Additionally, by supporting multi-issuance for some extended instructions, our processor can simultaneously support SIMD and MIMD operations, significantly improving the IPC of the pipeline. Our experimental results demonstrate that our design achieves excellent performance across various in-network computing applications. In terms of area efficiency, our processor shows improvements ranging from 2.0 to 36.3 times compared to the current state-of-the-art processors. These results highlight the effectiveness of our proposed techniques in enhancing both performance and efficiency for data-intensive applications.