Fpga-Based Yolov5s Accelerator With Hybrid Compression Approach

To realize the deployment of YOLOv5s object detection model on resource-limited edge devices, this paper proposed a YOLOv5s acceleration approach based on hardware and software co-design. Firstly, this paper proposes a hybrid compression strategy that combines L1 regularization-based pruning and quantization at the software level, effectively reducing model parameters volume for hardware deployment. Then a hardware acceleration architecture is designed. The proposed accelerator specially utilizes Processing Elements (PE) arrays that are compatible with different convolution modes and supports different levels of parallelism, in order to improve the inference speed of the model. The experimental results show that the hybrid compression approach achieved 90 % parameters reduction but only 0.8 % accuracy loss. Moreover, the accelerator achieved 646.6 GOPS at 150 MHz and realized about <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$45 \times$</tex> speedup ratio compared with CPU. It also improves energy efficiency and DSP efficiency compared to existing approaches.