Dipole Engineered Gate Stacks in AOS Channel FETs to Overcome the V_T-I_ON Tradeoff

Amorphous oxide semiconductor (AOS) based channels such as tungsten doped In<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> (IWO) [1] are potential candidates for back end of the line (BEOL) compatible transistors to enable monolithic 3D integration of logic and memory [2]. However, the threshold voltage ($\mathrm{V}_{\mathrm{T}}$) for AOS FETs are commonly reported to be negative and, therefore, fail to operate as enhancement mode devices [3]. The common techniques to modulate the $\mathrm{V}_{\mathrm{T}}$ for AOS-FETs include channel cation doping [4–6], channel thickness scaling [7, 8], and rapid thermal annealing (RTA) in O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> ambiance [3, 9] (Fig. 1a-c). However, these traditional methods come at the expense of performance degradation with Ion decreasing as the $\mathrm{V}_{\mathrm{T}}$ is increased. In this work, dipole engineered gate stacks (Fig. 1d) are investigated to overcome the fundamental $\mathrm{V}_{\mathrm{T}}-\mathrm{I}_{\mathrm{ON}}$ tradeoff in AOS FETs (Fig. 2). We demonstrate a dipole engineered gate stack with a +270 mV positive shift in $\mathrm{V}_{\mathrm{T}}$ and $0 \%$ Ion degradation.