Comprehensive Evaluation of Device Parameter Variations and Their Impact on 8nm Gate Length SOI n-FinFET Performance Characteristics

This paper presents an in-depth investigation into the electrical behavior of a Silicon-On-Insulator (SOI) n-type Fin Field Effect Transistor (n-FinFET) featuring an 8 nm gate length. The analysis is carried out using Technology Computer-Aided Design (TCAD) simulations to evaluate key performance parameters such as threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>), gate work function variations, transconductance (g<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf>), and output characteristics, including Drain-Induced Barrier Lowering (DIBL). The simulations are performed using the SILVACO TCAD tool for a 3D SOI n-FinFET at 300K [1].The results emphasize the influence of short-channel effects (SCEs)—particularly DIBL—on the overall device performance at the nanometer scale. Special focus is given to examining how modulation in gate metal work function (Φ<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf>) affects the threshold voltage and leakage current. The findings reveal that a reduction in gate metal work function leads to a decrease in V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>, which in turn affects leakage characteristics. Interestingly, an increase in Φ<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> contributes to better leakage control due to improved electrostatic behavior.Overall, the study demonstrates that short-channel effects in advanced 3D SOI FinFETs can be effectively mitigated by optimizing the gate material properties, particularly the metal work function. These insights are valuable for the design and development of next-generation low-power and high-performance FinFET technologies in nanoelectronic applications.

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Published
2025-06-05
DOI
https://doi.org/10.1109/eaic66483.2025.11101387
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
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article
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article

Comprehensive Evaluation of Device Parameter Variations and Their Impact on 8nm Gate Length SOI n-FinFET Performance Characteristics

Gagnesh Kumar, Sahil Koundal
Advancements in Semiconductor Devices and Circuit Design
article

Comprehensive Evaluation of Device Parameter Variations and Their Impact on 8nm Gate Length SOI n-FinFET Performance Characteristics

Gagnesh Kumar, Sahil Koundal
article en

Abstract

This paper presents an in-depth investigation into the electrical behavior of a Silicon-On-Insulator (SOI) n-type Fin Field Effect Transistor (n-FinFET) featuring an 8 nm gate length. The analysis is carried out using Technology Computer-Aided Design (TCAD) simulations to evaluate key performance parameters such as threshold voltage (V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>), gate work function variations, transconductance (g<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf>), and output characteristics, including Drain-Induced Barrier Lowering (DIBL). The simulations are performed using the SILVACO TCAD tool for a 3D SOI n-FinFET at 300K [1].The results emphasize the influence of short-channel effects (SCEs)—particularly DIBL—on the overall device performance at the nanometer scale. Special focus is given to examining how modulation in gate metal work function (Φ<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf>) affects the threshold voltage and leakage current. The findings reveal that a reduction in gate metal work function leads to a decrease in V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</inf>, which in turn affects leakage characteristics. Interestingly, an increase in Φ<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> contributes to better leakage control due to improved electrostatic behavior.Overall, the study demonstrates that short-channel effects in advanced 3D SOI FinFETs can be effectively mitigated by optimizing the gate material properties, particularly the metal work function. These insights are valuable for the design and development of next-generation low-power and high-performance FinFET technologies in nanoelectronic applications.

National Institute of Technology Hamirpur (BD)
Affordable and clean energy
Openalex Percentile: Top 81%
Advancements in Semiconductor Devices and Circuit Design
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Comprehensive Evaluation of Device Parameter Variations and Their Impact on 8nm Gate Length SOI n-FinFET Performance Characteristics — Gagnesh Kumar, Sahil Koundal · (2025) | TGRS Research Map | TGRS