20-50 nm Channel Length Single-Gate a-IGZO TFTs with Superior Gate Control and Reduced Short-Channel Effects

Short-channel amorphous oxide thin-film-transistors (TFTs) are promising candidates for Back-End-OfLine (BEOL) applications owing to low off-state current, high on-state current and low-temperature compatible fabrication processes. [1–4] As scaling down channel length ( $L_{c h}$ ) to improve device performance such as speed and oncurrent, it is important to scale down characteristic length ( $\lambda$ ) simultaneously to avoid short channel effect. It has been reported that $L_{c h}$ needs to be at least $\times 5 \sim \times 10$ larger than $\lambda$ (i.e., $L_{c h} / \lambda\gt5 \sim 10$ ) for effective gate control over channel. [5] When $L_{c h}, t_{\text {channel }}$ and $t_{\text {oxide }}$ are scaled down to few nm, $L_{c h} / \lambda$ can become small (e.g., $L_{c h} / \lambda\lt5$ ) and device tends to suffer from short channel effects (SCEs) which might require using a second gate to reduce $\lambda$ further. Our group has recently proposed a device architecture based on nanospike electrodes that has excellent performance at very short channel lengths. In this work, we extend this down to $\sim 20 \mathrm{~nm}$ channel length and show that even at such channel lengths, which result in a ( $L_{c h} / \lambda$ ) ratio of $\sim 2.2$, which is a very small value, excellent gate control, sub-threshold characteristics, and suppression of short channel effects are achieved. These characteristics result from the gate field controlling the channel laterally as well as vertically. For example, the DIBL in a 20 nm TFT with the new architecture is comparable in magnitude to the DIBL in a 90 nm TFT with a conventional single-gate geometry. Thus, the unique device geometry facilitates quasi-3D gate control, including control from the sides of the channel. This design concept can also be applied to other semiconductor based TFTs as well and can be applicable to double-gate structures as well.