ITO Contact Optimization for Enhancement Mode BEOL MOSFETs

Monolithically integrated active components that are post-CMOS compatible enable to shift several functionalities to the back-end-of-line (BEOL), for example; power gating, voltage regulation, analog RF transistors, and non-volatilememories (NVM). This approach could offer both higher performance and overall denser integration. Oxide semiconductors (OS), such as tin-doped-InO ${ }_{\mathrm{x}}$ (ITO), represent an interesting set of materials for BEOL integration as they, compared to Si and Si-on-insulator (SOI), have advantageous electrical properties and can be deposited onto many different types of surfaces at low temperatures (low-T), using physical vapor deposition (PVD) or atomic layer deposition (ALD). The spherical symmetry of the s-orbital dominated conductance makes OSs insensitive to roughness and defects [1], allowing high mobility ($\mu_{\mathrm{FE}}\gt100 \mathrm{~cm}^{2} \mathrm{~V}^{-1} \mathrm{~s}^{-1}$) for thin films ($\gt1.5 \mathrm{~nm}$) [2]. Further, the wide bandgap and low achievable contact resistances ($R_{\mathrm{C}}$), combined with the relatively shallow electric field penetration depth due to low permittivity, means that high performance can be achieved with very aggressively scaled devices [3]. Demonstrations show large ON/OFF-current ($I_{\text {on }} / I_{\text {off }}$) ratios of $10^{10}$ for a channel length ($L_{\mathrm{G}}$) of 10 nm [4], and high $I_{\text {on }}$ of $3.1 \mathrm{~mA} / \mu \mathrm{m}$ for 0.5 V drain-source-voltage ($V_{\mathrm{DS}}$) [2]. The best demonstrated contact resistance reaches the quantum limit at $R_{\mathrm{c}}=23.4$ $\Omega \mu \mathrm{m}$, with a negative Schottky barrier due to trap-induced positive charges at the $\mathrm{InO}_{\mathrm{x}}$ contact interface [5], improving on the previous record low $R_{\mathrm{C}}$ of $162 \Omega \mu \mathrm{~m}$ for ITO [4]. It is further laid out that a 2D carrier density of $\sim 2 \cdot 10^{13} \mathrm{~cm}^{-2}$ is needed to reach quantum limit resistance, which for the devices in the study, pushes the threshold voltage ($V_{\mathrm{T}}$) into deep negative bias [4]. In this work, we show how a low $R_{\mathrm{C}}$ can be combined with enhancement operation.