Low-Power Non-Volatile Flip-Flop Design Using NAND-Spin Logic for Energy Efficient Systems

Non-Volatile Flip-Flops (NVFFs) are intended for addressing the growing leakage power consumption problem linked with CMOS technology advancements. As complexity increases, power dissipation has become a key design restriction. The demand for quick, low-power devices and digital circuits has increased rapidly during the past several years. The use and exploitation of the FF have gained popularity in the research area of low-power and voltage VLSI circuits at the gate level, as well as low-power applications systems. Power Gating (PG) techniques in NVFFs have the ability to solve the rising leakage power consumption problem caused by CMOS (Complex Metal Oxide semiconductor) technology advancement. The MTJs is excellent in developing the NVFF due to its less power consumption, fast efficiency, and greater CMOS integration. A new magnetic NVFF based on NAND-SPIN, a recently created storage technology. By using the SPIN Orbit Torque (SOT) and Spin Transfer Torque (STT) the data erasing function and the programming functions are done respectively. The feature enables us to create a magnetized NVFF that is both erasehidden and improves drivability. Moreover, it can be done by the principle of shorted gate FINFET logic, which intends to improve the noise factor, and achieve high write speeds and endurance. Furthermore, the study will address scalability difficulties at the nanoscale. According to simulation results, the suggested NVFF outperforms the traditional slave- latchdriven, hold-up time, and power.