Design criteria for Short-Channel Effect Mitigation through Optimized Source/Drain Electrode in Highly Scaled a-IGZO TFTs

Amorphous oxide thin-film transistors (TFTs) are being explored as promising candidates for Back-End-Of-Line (BEOL) transistors and next-generation memory components due to their low off-state current, high on-state current ($I_{\mathrm{ON}}$), and low integration process temperature [1], [2]. However, reducing the channel length ($L_{\mathrm{ch}}$) of transistors decreases the $L_{\mathrm{ch}}$ to characteristic length ($\lambda$) ratio ($L_{\mathrm{ch}} / \lambda$), leading to significant degradation in short channel effects (SCEs) such as drain-induced barrier lowering (DIBL) and subthreshold swing (SS). This degradation is primarily due to the loss of gate control at the channel’s top surface. Therefore, scaling $\lambda$ is crucial alongside $L_{\mathrm{ch}}$ scaling. This can generally be achieved by: 1) reducing the gate oxide thickness ($T_{\mathrm{ox}}$), 2) employing high-k dielectrics ($\varepsilon_{\mathrm{ox}}$), or 3) decreasing the channel thickness ($T_{\mathrm{ch}}$), as $\lambda=\sqrt{T_{\mathrm{ch}} \cdot T_{\mathrm{ox}} \cdot \varepsilon_{\mathrm{ch}} / \varepsilon_{\mathrm{ox}}}$. Recent approaches have reduced the channel thickness $T_{\mathrm{ch}}$ to reduce $\lambda$. However, extremely scaled device structures will eventually face physical scaling constraints, which can impair device performance, causing non-idealities such as gate leakage, threshold voltage ($V_{\text {th }}$) shifts, or even loss of semiconductor functionality.