Optimization is Key to High-Temperature Reliability in Oxide-Semiconductor FETs

Oxide semiconductor field-effect transistors (OSFETs) with back-end-of-line compatibility and ultralow leakage have potential for high-density on-chip memories. Two-transistor gain-cell (GC) memories, where write and read transistors share a storage node, are attractive for global buffers in TPU-like systolic arrays and KV cache for large language models [1]–[3]. However, repeated read/write operations and standby state cause prolonged bias stress and device self-heating, resulting in progressive negative threshold voltage shifts $\left(\Delta \mathrm{V}_{\mathrm{T}}\right)$. In this work we investigate the positive bias stress (PBS) stability from below room temperature ($-15^{\circ} \mathrm{C}$) to high temperatures ($85^{\circ} \mathrm{C}$) in atomic-layer-deposited Indium Tungsten Oxide (IWO) FETs with standard HfO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> and optimized gate dielectric ($\mathrm{D}_{\text {std }}$) and ($\mathrm{D}_{\text {opt }}$), respectively. We define a “critical temperature” ($\mathrm{T}_{\text {crit }}$)- the point at which hydrogen release mechanism overtake deep-electron trapping and show that $\mathrm{D}_{\text {opt }}$ with $\mathrm{T}_{\text {crit }}$ near $85^{\circ} \mathrm{C}$ exhibits significantly lower $\Delta \mathrm{V}_{\mathrm{T}}$ at $85^{\circ} \mathrm{C}$ compared to $\mathrm{D}_{\text {std. }}$ Further analysis reveals that very high T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</inf> values (e.g., $125^{\circ} \mathrm{C}$) increase temperature sensitivity highlighting the importance of designing OSFETs around an optimal T<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">crit</inf> for reliable, high throughput data buffering.