Memory Window Improvement by Contact Depinning in Al_1-xB_xN FeFETs with ZnO Semiconductor Channel

Growing interest in nonvolatile memory compatible with back-end-of-line integration has driven advancements in ferroelectric field-effect transistors (FeFETs) with oxide semiconductors. Recently, we demonstrated $15 \mathrm{~nm} \mathrm{Al}_{1-\mathrm{x}} \mathrm{B}_{\mathrm{x}} \mathrm{N}$ FeFETs with ZnO semiconductor channels, but the memory window (MW) was small, $\sim 1 \mathrm{~V}$ at room temperature, due to a negative shift in the turn-on voltage ($\mathrm{V}_{\text {on }}$) with cycling, as shown in Fig. 3 [1]. We attribute this shift to the thinfilm transistor structure. For sufficiently large $+V_{G S}$, polarization in the $\mathrm{Al}_{1-x} \mathrm{~B}_{x} \mathrm{~N}$ layer from source to drain can be switched upward due to electron accumulation in the ZnO channel. However, for $-\mathrm{V}_{\mathrm{GS}}$, the $\mathrm{Al}_{1-\mathrm{x}} \mathrm{B}_{\mathrm{x}} \mathrm{N}$ polarization can only be switched downward in the FET contact regions. Because holes are not accumulated in the ZnO, the electric field in the channel region (between contacts) is not confined. In this region, once switched upward, the polarization will remain in this state. The unswitched polarization results in a negative shift in the gate voltage required for electron accumulation in the channel region (between the contacts). Combined with significant electron density at the source and drain metal contacts due to Fermi level pinning near the ZnO conduction band minimum at the $\mathrm{ZnO}-\mathrm{Ti}$ interface ($\mathrm{E}_{\mathrm{C}}-\mathrm{E}_{\mathrm{F}} \sim 0.1 \mathrm{eV}$), this results in a negative shift in the threshold and turn-on voltages for the FeFET (Fig. 5). By introducing a thin Al<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> dielectric layer between the ZnO channel and Ti source/drain contacts, we are able to unpin the Fermi level, resulting in a large increase in memory window (to $\sim 10 \mathrm{~V}$ for FeFETs with 15 nm thick $\mathrm{Al}_{1-\mathrm{x}} \mathrm{B}_{\mathrm{x}} \mathrm{N}$ and 10 nm thick ZnO channel).