Design, Investigation and Spacer optimization of a Tri metal- Stacked Gate Si-SiGe GAA cylindrical- Nanotube Field Effect Transistor (TM-SG-NTFET)

In the manuscript, a novel Tri metal- Stacked Gate Si-SiGe GAA Nanotube FET is proposed. The proposed structure has a tabular 3D structure, consist of inner and outer gates to increase the electrostatic control over channel region and to generate effective charge control thus providing the Nanotube FET excellent immunity to short channel length problem. The proposed device uses tri gate structure with different metals along with gate stacking technique for better electrostatic behavior. The device physics is elaborated with the help of various device parameters like e/h concentration, EBD and e field. The proposed device offers good analog parameters like high on current (1.46*10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> A), less off current (3.87*10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-13</sup> A), good Ion/Ioff ratio (3.77*10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup>) and transconductance (8.84*10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-5</sup> S). The effect of gate metal work function variation on the performance of the device is also evaluated and to optimize the gate metal work function combination. The spacer plays a vital role in optimizing the lateral electric field for better analog performance. The effect of various spacer materials and spacer length is also studied in the manuscript.